The present disclosure herein relates to a cache memory, and more particularly, to a cache memory device and an operating method thereof.
A cache memory is a high-speed memory that is located between a processor and a system memory in order to supplement the operating speed between the processor and the system memory (e.g., SDRAM). The cache memory may temporarily store a command or data that is requested by the processor.
In the case where the command or data stored in the cache memory has an error by various factors, the processor may receive the command including the error from the cache memory and thus cause malfunction. Thus, various techniques for detecting or recovering the error that the cache memory has are being developed.